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Seminars given
February 01, 2006 - Understanding Cache Attack
by Cédric Lauradoux
| Abstract: | Recently a lot of works have investigated the possibility to exploit the cache memories to mount side channel attacks against encryption system on superscalar processors. In a first part, I will show some simple ways to evaluate the impact of cache memory on a process execution. The effects of cache memories on processor performance have been well studied by the micro-architecture community. The reference documents in the study of cache memory are the works of Hill. We have tried to unify those works and cache miss attacks. As a result, I will present a classification of the known cache miss attacks according to the 3C of Hill. The second part of my talk will be devoted to the AES study case. Wewill show the impact of the overall micro-architecture of a processor on the AES cache attacks.The possibilities to defeat cache miss attacks are numerous. For instance, we can use compensation loop to average the timing of the AES. But the overhead induced by this solution is too important (indeed we reach the Worst Case Execution Time). I will present a countermeasure very similar to masking that can defeat all known cache attacks against the AES with a low overhead (<5%).
Joint work with Anne Canteaut and Andre Seznec
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