@ARTICLE{cgUCL-BBMSTT18,
 	AUTHOR={Bellizia, Davide and Bongiovanni, Simone and MonsurrĂ², Pietro and Scotti, Giuseppe and Trifiletti, Alessandro and Trotta, Francesco Bruno},
	TITLE={{Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks}},
	JOURNAL={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	VOLUME={26},
	PAGES={1368-1376},
	MONTH={3},
	YEAR={2018},
}

@INPROCEEDINGS{cgUCL-BMT17,
 	AUTHOR={Bellizia, Davide and MonsurrĂ², Pietro and Trifiletti, Alessandro},
	TITLE={{VHDL implementation of FWL RLS algorithm}},
	BOOKTITLE={2017 European Conference on Circuit Theory and Design (ECCTD)},
	PUBLISHER={IEEE},
	MONTH={11},
	YEAR={2017},
}

@ARTICLE{cgUCL-BBMST16,
 	AUTHOR={Bellizia, Davide and Bongiovanni, Simone and MonsurrĂ², Pietro and Scotti, Giuseppe and Trifiletti, Alessandro},
	TITLE={{Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications}},
	PUBLISHER={IEEE},
	JOURNAL={IEEE Transactions on Emerging Topics in Computing},
	VOLUME={5},
	PAGES={329-339},
	MONTH={5},
	YEAR={2016},
}