@INPROCEEDINGS{cgUCL-BPST18,
 	AUTHOR={Bellizia, Davide and Palumbo, Gaetano and Scotti, Giuseppe and Trifiletti, Alessandro},
	TITLE={{A Novel Very Low Voltage Topology to implement MCML XOR Gates}},
	BOOKTITLE={ 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
	PUBLISHER={IEEE},
	MONTH={8},
	YEAR={2018},
}

@ARTICLE{cgUCL-BSPT17,
 	AUTHOR={Bellizia, Davide and Scotti, Giuseppe and Palumbo, Gaetano and Trifiletti, Alessandro},
	TITLE={{Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies}},
	JOURNAL={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	VOLUME={25},
	PAGES={3509-3520},
	MONTH={9},
	YEAR={2017},
}