@INPROCEEDINGS{cgUCL-BMT17,
 	AUTHOR={Bellizia, Davide and MonsurrĂ², Pietro and Trifiletti, Alessandro},
	TITLE={{VHDL implementation of FWL RLS algorithm}},
	BOOKTITLE={2017 European Conference on Circuit Theory and Design (ECCTD)},
	PUBLISHER={IEEE},
	MONTH={11},
	YEAR={2017},
}